Suppression of transients or glitches

Status
Not open for further replies.
S

suhas_shiv

Full Member level 2
Joined
Nov 30, 2005
Messages
136
Helped
11
Reputation
22
Reaction score
4
Trophy points
1,298
Activity points
2,461
I am designing a Pipeline ADC. I want to suppress/eliminate any transients/glitches that occur at reference voltage nodes (used in the ADC comparators mainly). Apart from putting in a capacitor, what other circuit can I use? Any precautions to be taken? If anybody could upload papers or give me ideas, I would appreciate.

Thanks,

Suhas
 

hi
maybe you can design LDO it can remove the high freuqency noise on vdd or vss
 

You would need a reference buffer with fast-settling time.

An alternative is to use a large off-chip capacitor.
 

Status
Not open for further replies.

Similar threads

Menu
Log in
Register
Cookies are required to use this site. You must accept them to continue using the site. Learn more…