Suppression of transients or glitches

[suhas_shiv]

I am designing a Pipeline ADC. I want to suppress/eliminate any transients/glitches that occur at reference voltage nodes (used in the ADC comparators mainly). Apart from putting in a capacitor, what other circuit can I use? Any precautions to be taken? If anybody could upload papers or give me ideas, I would appreciate.

Thanks,

Suhas

 

[zyyang]

hi
maybe you can design LDO it can remove the high freuqency noise on vdd or vss

 

[elbadry]

You would need a reference buffer with fast-settling time.

An alternative is to use a large off-chip capacitor.