I am looking for a Graphical VHDL Editor. I have build varius VHDL modules and i want to create multiple instances of them and connect them in pure-structural manner at top-level. I wish to avoid instantiating them by hand because it is confusing and error prone . I have tried to instantiate them using the generate vhdl feature, but the structures are not regular , so there no use for it.
If you hava any suggestion please post it, free tools would be preferable.
Many thanks
I have studied such topic for years. The traditional schematic based tool usually cannot fit for large project.
I think the best one is Topweaver. It is free. Visit http://www.topweaver.com/demo.htm for quick demos.