subthreshold bandgap refernece design

[Akshe]

Subthreshold bandgap reference design

Hi All,

I am new to design and have been working on designing a low power bandgap reference circuit using subthreshold transistors for my college project. The design is based on a reference paper and i am trying to implement it on a different technology node. But i am unable to achieve the desired results.

I believe i am unable to size the devices appropriately and hence not getting the expected results. Currently i have tried two approaches for sizing - 1) Using the mentioned sizes in the paper 2) Starting from some scratch values and trying to use the equation to match the values. But with both i am unable to get results.

The design is as below:



Ref. Paper - JSSC Jul 09 - A 300 nW 15 ppmC 20 ppmV CMOS Voltage Reference Circuit Consisting of Subthreshold MOSFETs
View attachment JSSC Jul 09 - A 300 nW 15 ppmC 20 ppmV CMOS Voltage Reference Circuit Consisting of Subthreshold.pdf

Technology and specifications - 130nm process, BSIM4 model, Supply voltage- 0.9-1.5 V, 1.2V transistors
According to calculations and as per threshold modelling in BSIM4 the corresponding reference voltage should be nearly around 560mV.

The results that i obtain with the two approaches are as seen in the images..

1) Using Paper sizes



2) Using sizes from scratch



It would be of immense help to me if someone could help me in progressing with this as i have been stuck with this for a very long time now :sad:

 

[erikl]

Re: subthreshold bandgap reference design

Not simple to give an unambiguous answer why your κ is a factor of 15 larger. Just 2 hints:

1. You didn't (yet) use the OTA buffer (M10 - M14 in fig. 3 of the a.m. paper)
2. The M_R1 transistor (your 4-fold N3a - NM37 chain, W/L≈1/4) is by far not working in strong inversion mode (should operate in triode mode, as a resistor). Check its operating point (Vds)!

 

[Akshe]

Re: subthreshold bandgap reference design

I did try using the OTA in the design but couldn't achieve a significant difference in results actually.
Also for the operating points of the MR1 transistor i had used the region option while displaying the DC operating points and it showed the region as 1 (linear)..

Could this issue be also because of some architecture limitation ?

 

[amitjagtap]

Using OTA for biasing is not good...For BandGAP circuit itselt you are using one more OTA...THis is something not good...
About design... Confirm the operating point of all MOSFETs as all should be in subthreshold region...
Best method to design low power subthreshold circiut is gm/Id method...Comparatively you will get w/L ratios faster and more optimised...
check for this method..
You have not included start up circuit in your design....

 

[Akshe]

Could you please elaborate a little about the gm/Id method?
Ya have not included the startup as of now, was trying to get the core working first ..