substrate coupling isolation of passive devices in cmos

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angyp

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what is the best way to isolate passive elements like capacitors from a sensitive circuitry on the chip? if i group up few capacitors and place them at the corner of the chip, how do i isolate those capacitors from the circuit?
 

If your thecnology permits you can use a well. You can implement the passive elements in a well.
 

There are some special process level solutions: heavily-doped substrate, SOI, burried layers, extra wells etc, but they are much more expensive.

Layout solutions: for heavily-doped substrate you can try to increase the distance between the noise sources and noise victims. For Lightly-dope substrate a guard ring works well.

Which ciruit are you designing? I am not an expert in this area - but does the capacitor makes so much noise? Usually people are companing about separating RF/analog from digital parts.
 

could anyone pls. elaborate me how an epi layer(lightly doped,high resistivity) is more immune to latch-up problem?
 

usually epi-layer is used with heavy-doped and low resistivity buried layer.
 

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