AllenD
Member level 5
Hi Team
I am using TSMC 65nm 0V-1.2V technology to tape out an IC. I created a filler cell with substrate contact as this.
1. Create a unit filler cell with a unit layout connect M1,3,5,7 to gnd and M2,4,6 to vdd
2. Add substrate contact form M1 to gnd.(I heard there is no such thing as too much substrate contact)
3. Fill the opening in your layout with this small unit filler.
So all my psub is connected to a good gnd. However, when I added the TSMC ESD devices, there is an error in LVS.
WARNING: Stamping conflict in SCONNECT - Multiple source nets stamp one target net.
I suspect it is due to the substrate connect (error will disappear when I remove the substract contact). The ESD device has it's own substrate contact connected the psub at a different voltage then gnd....Therefore in my layout, the sub is connected to 2 different voltage pin through substrate contact.
Can anyone have any idea how to solve this problem?
Thanks Allen
I am using TSMC 65nm 0V-1.2V technology to tape out an IC. I created a filler cell with substrate contact as this.
1. Create a unit filler cell with a unit layout connect M1,3,5,7 to gnd and M2,4,6 to vdd
2. Add substrate contact form M1 to gnd.(I heard there is no such thing as too much substrate contact)
3. Fill the opening in your layout with this small unit filler.
So all my psub is connected to a good gnd. However, when I added the TSMC ESD devices, there is an error in LVS.
WARNING: Stamping conflict in SCONNECT - Multiple source nets stamp one target net.
I suspect it is due to the substrate connect (error will disappear when I remove the substract contact). The ESD device has it's own substrate contact connected the psub at a different voltage then gnd....Therefore in my layout, the sub is connected to 2 different voltage pin through substrate contact.
Can anyone have any idea how to solve this problem?
Thanks Allen