[SOLVED] Substitute for records structures of VHDL in Verilog

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ishan.dalal

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Hi,

I am working on converting a VHDL code which is heavy on records structures usage to verilog. It's a highly parameterized code using packages. I am also new to Verilog. Is there any substitute for records in verilog?
 

You should look at SystemVerilog which has structures and packages. This will make the conversion process a whole lot easier. Just make sure whatever tools you plan to use with the code can support it.
 

Hi Dave,

I need to use verilog since it's the requirement of the project. Is there any way I can parameterize the code in verilog? VHDL has packages, records which helps in parameterizing the code. How to do the same thing in verilog?
 

I think it will be easier to convince the person making the requirement to switch to SystemVerilog than it will be to convert the VHDL code to Verilog.

Converting a VHDL record to Verilog is very painful. You have to pack all the fields of a record into a single bit vector, and define part-select ranges for each field.

For example, This in VHDL

Code: 
type Operation is record
    OpCode : Bit_Vector(3 downto 0);
    Op1, Op2, Res : Bit_Vector(1 downto 0);
end record;
instr : Operation

instr.OpCode = "1010";

Becomes this in Verilog

Code: 
reg [9:0] instr; // width is the sum of all field widths
`define OpCode [9:6]
`define Op1 [5:4]
`define Op2 [3:2]
`define Res [1:0]

instr `Opcode = 'b1010;
 
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