subc connection, it is not right?

[shanmei]

From the thread, https://www.edaboard.com/threads/264917/

which shows NMOS bulk and sub! connection.



I am wondering the whether the connection is right. The trip well NMOS device is used to isolate the bulk node and the noisy sub! node. In the above figure, the bulk and sub! are actually shorted together though the subc.

1. Then how can the bulk immune from the noisy sub!?
2. We can assume that the two terminals of the subc are short, right?

Thanks.

 

[Dominik Przyborowski]

ad1. Note, that bulk terminal and substrate are connected through contacts and metal layer to ground potential (low impedance node forcing well defined potential). Between transistor body and chip substrate are two reversed diodes and this makes the job. You could saw it better with schematic for nfet with source terminal not connected to the ground.
ad2. Yes, in this example both nfet bulk and chip substrate are connected by metal paths together to VSSA node.

 

[dick_freebird]

The schematic of course is too simple to show the
reality of that routing and the routing of any noise
currents. Global nets are fine for circuits where this
does not matter. If you care, then care enough to
model such things at sufficient detail.

 

[shanmei]

Thanks. Now I understand it is because the VSSA is a low impedance node which forces the potential at bulk to be zero.