May 7, 2015 #1 ivlsi Advanced Member level 3 Joined Feb 17, 2012 Messages 883 Helped 17 Reputation 32 Reaction score 16 Trophy points 1,298 Activity points 6,868 Hi All, What is Stretched Synchronizer? How should it be implemented? Thank you!
May 7, 2015 #2 D.A.(Tony)Stewart Advanced Member level 7 Joined Sep 26, 2007 Messages 9,014 Helped 1,824 Reputation 3,647 Reaction score 2,202 Trophy points 1,413 Location Richmond Hill, ON, Canada Activity points 59,605 Is this to eliminate metastable errors (race) or stretch glitches?
May 7, 2015 #3 H harpv Member level 4 Joined May 30, 2012 Messages 73 Helped 19 Reputation 38 Reaction score 20 Trophy points 1,288 Activity points 1,838 Or do you mean to have a pulse synchronizer across clock domains?
May 7, 2015 #4 ivlsi Advanced Member level 3 Joined Feb 17, 2012 Messages 883 Helped 17 Reputation 32 Reaction score 16 Trophy points 1,298 Activity points 6,868 Stretched synchronizer - I mean synchronization of fast clock domain to a slow one -> what synchronizer should be used?
Stretched synchronizer - I mean synchronization of fast clock domain to a slow one -> what synchronizer should be used?
May 7, 2015 #5 D.A.(Tony)Stewart Advanced Member level 7 Joined Sep 26, 2007 Messages 9,014 Helped 1,824 Reputation 3,647 Reaction score 2,202 Trophy points 1,413 Location Richmond Hill, ON, Canada Activity points 59,605 ivlsi said: Stretched synchronizer - I mean synchronization of fast clock domain to a slow one -> what synchronizer should be used? Click to expand... Subharmonic sync? Use divider to generate slow clock or PLL or use system clock with 2 stage FF to avoid races on async clocks. If worried about aliasing effects, eg slow data sent on high speed bus, use FF to send a 1 once only. Such as for PWM or tach out. But your case is fast to slow so must use clock at least 2x data rate and 2 stage FF for capture without loss of data or glitches.
ivlsi said: Stretched synchronizer - I mean synchronization of fast clock domain to a slow one -> what synchronizer should be used? Click to expand... Subharmonic sync? Use divider to generate slow clock or PLL or use system clock with 2 stage FF to avoid races on async clocks. If worried about aliasing effects, eg slow data sent on high speed bus, use FF to send a 1 once only. Such as for PWM or tach out. But your case is fast to slow so must use clock at least 2x data rate and 2 stage FF for capture without loss of data or glitches.