Stretched Synchronizer - what is it?

[ivlsi]

Hi All,

What is Stretched Synchronizer? How should it be implemented?

Thank you!

 

[D.A.(Tony)Stewart]

Is this to eliminate metastable errors (race) or stretch glitches?

 

[harpv]

Or do you mean to have a pulse synchronizer across clock domains?

 

[ivlsi]

Stretched synchronizer - I mean synchronization of fast clock domain to a slow one -> what synchronizer should be used?

 

[D.A.(Tony)Stewart]

Stretched synchronizer - I mean synchronization of fast clock domain to a slow one -> what synchronizer should be used?

Subharmonic sync? Use divider to generate slow clock or PLL or use system clock with 2 stage FF to avoid races on async clocks.


If worried about aliasing effects, eg slow data sent on high speed bus, use FF to send a 1 once only. Such as for PWM or tach out.

But your case is fast to slow so must use clock at least 2x data rate and 2 stage FF for capture without loss of data or glitches.