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strange postsimulation results

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lhlbluesky

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i use calibre PEX for my layout postsimulation, but i find a strange problem.

for sub-block A and sub-block B, when i extract the separate PEX calibreview for A and B, and simualte, the results are very bad, resolution from 10bit(presimulation) to 6bit(postsimultion) or less; while, after i make one subcircuit with A and B (for ex: called C, C contains two sub-block calibreview A and B) and simulate, the results improve a lot, resolution from 10bit(presimulation) to 8bit(postsimultion) or so; why? what is the reason?

if i want to see one sub-block's performance(for ex: A) by postsimulation, then what should i do? if i use calibreview of A and other sub-blocks with schematic in presimulation(without parasitics), then run simulation with a config testbench, is the postsimulation result reliable? or any other ways available?

besides, if i use some sub-blocks' calibreview and the other blocks' schematic view in presimulation, and run simulation for my whole circuit, then the results reliable?

finally, how to optimize the layout for better circuit performance? how to fix the main affecting wires and nets in layout?

pls help me,thanks in advance.
 

Old Nick

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I guess your on about post-layout simulation, and pre-layout simulation.

I would need to see your schematic, layout and simulation files etc. before I could comment on the reasons for poor performance.

However, your post layout simulation should be the more accurate of the two.

To improve performance, follow good layout guidelines, try and separate analogue and digital blocks/interconnects as much as possible. Look at the extracted parasitics, and try to minimize capacitance and resistance of tracks, use common centroid layouts.
Also perform noise simulations to find poor performing blocks, change transistor sizing etc. to minimize etc.
 

lhlbluesky

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but for a short wire in layout, there are lots of parasitic resistor and cpacitor, and i can't identify them, and don't know how to minimize them, is there any method?
besides, as you say, perform noise simulations to find poor performing blocks, but how to do this?
how to do noise simulations for my circuit? and transient noise or frequency noise? and how to find poor performing blocks according to noise simulations? pls help me again. thanks.
 

davidli

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I think it is up to what kinds of circuit, maybe the loads are different and then the results are different
 

lhlbluesky

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also the same question: how to optimize the layout for better circuit performance and lower parasitic effect? and what kind of parasitics are the main affecting factor for circuit performance degration, and how to find them?
 

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