Strange coupling behavior between transistors in ADS simulation

[DoYouLinux]

Hi all,

I am very curious about a schematic simulation. In ADS 2012, I tried to simulate an S parameter of a single-stage common-emitter amplifier. This amplifier consists of only 1 transistor (BJT). Then, I just added another BJT, which every terminal is connected to ground (let's call this a Dummy BJT).

Surprisingly, the S parameter results before I added the Dummy BJT and after are not the same. It is not so much, for example, impedances corresponding to S11_before = 30 + j20 and that of S11_after = 35 + j22. But, this Dummy BJT should not lead to any affect and the results between before and after adding it should be the same. I am wondering about the substrate ... the BJT has 3 terminals and when open its property window, I saw the body node = sub is written ....

Any idea ????

DYL

 

[dick_freebird]

Yes, many CAD systems allow inherited nets or other invisible
connections. If you let this go unchecked it can surprise you.
And I've seen libraries where the 4th terminal is tied to a large
negative or positive voltage with some device params given
dummy values, the thinking being this would "kill" some features
that smart guys who never designed a circuit believed were
not relevant. Until you try to do low current analog and see
that KCL seems to be violated, and find out that even
dummied-out D-B and S-B diodes are conducting nanoamps
from "nowhere".

Now there is always a 4th terminal in a MOSFET. It may be
the substrate or it may be a little body pocket that comes and
goes with bias, or anything in between. A three terminal
approximation is just that, dependent on what you do to
make the body and source dead electrically equal. A BJT
in integrated circuit technology also likely has at least a 4th
terminal (outside of some SOI types where only a capacitor
connects collector and substrate). Most BJT models support
the 4th, ohmic (diode) terminal.

I'd bet that "sub" wants some realism applied. What this
means comes down to cases. Consider your technology's
cross-section construction and try to represent its likely
electrical attributes (potential, resistance between that
source and the devices and each other - a nasty little
mesh at anything above trivial complexity).

 

[FvM]

You are able to determine which circuit has been actually simulated by reviewing the generated netlist.

 

[DoYouLinux]

Hi all,

Thanks a lot for the suggestions. Yes, I forgot to check the netlist, and after that found that I need to connect the substrate correctly. It does take sub connection into account. Wow, this can be dangerous since there is no warning from the simulator.

DYL