Strange calculation of numbers in VHDL code

i am disassembling and studying processor bus code, and there are some strange things in a VHDL code.

For example, take a look at the following declaration:

signal Dreord: std_logic_vector(0 to C_DW*((C_NB+1)/2)*2-1);

C_DW and C_NB are generics of an entity, and their values are:
C_DW = 2
C_NB = 4

According to these generic values, the range of the Dreord signal should be:

2 * ( ((4 + 1)/2) * 2 - 1 ) = 8

So the range of the Dreord signal is 0 to 8. [magnitude is 9] However, according to the code, i see that it should be 0 to 7.

Also, when i simulate this code in ModelSim, it also says that the range is 0 to 7. So... why is this so? is there some thing to mention during the division calculation in VHDL code? i reviewed VHDL books but did not find anything special about it... however, i see that ModelSim counts it as 7, but actually it is 8...

Look at another piece of code:
CYMUX_FIRST: MUXCY
port map (CI=> zero,
DI=> one,
S=>lutout(i*(C_NB+1)/2),
O=>cyout(i*(C_NB+1)/2));

Here, when the variable i = 1, the expression in the brackets of cyout is: 1 * (4 + 1)/2 = 2.5 And it is also strange, why not integer number?...

cyout is declared as:
signal cyout: std_logic_vector(0 to (C_DW*(C_NB+1)/2)-1); [0 to 4]

so to which digit will the O output of the MUXCY element be assigned? cuz it is 2.5 :?:

2 * ( ((4 + 1)/2) * 2 - 1 ) = 8

Click to expand...

No, the correct result is seven. Please consider that (4+1)/2 = 2 in integer arithmetics.

There are only two of the "(" characters between * and C_NB.
The corrected grouping

2 * ((4 + 1)/2) * 2 - 1

evaluates to 7.