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Strange behavior of X-HDL

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Full Member level 5
Apr 19, 2002
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I try the X-HDL 3.2.21 release from x-tek (h**p://www.x-tekc0rp.c0m),
and get the following result.

Test: VHDL to Verilog translation
Input: D flip-flop entity (DFF.vhd)
Ouput: D flip-flop module (DFF_D.v)

-- Input: DFF.vhd --
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;

entity DFF is
generic(N : integer := 8);
port(CLK : in std_logic;
RSTB : in std_logic;
D : in std_logic_vector(N-1 downto 0);
Q : out std_logic_vector(N-1 downto 0));
end DFF;

architecture DFF_A1 of DFF is
dff_proc:process(RSTB, CLK)
if(RSTB='0') then
Q <= (others=>'0');
elsif(CLK'event and CLK='1') then
Q <= D;
end if;
end process dff_proc;
end DFF_A1;

// output: DFF_D.v
module DFF (CLK, RSTB, D, Q);

parameter N = 8;
input CLK;
input RSTB;
input[N - 1:0] D;
output[N - 1:0] Q;
reg[N - 1:0] Q;

always @(RSTB or CLK)
begin : dff_proc
if (RSTB == 1'b0)
Q <= {1{1'b0}} ;
else if (CLK == 1'b1)
Q <= D ;

// Expected result
module DFF(D, CLK, RSTB, Q);
parameter N=8;
input [N-1:0] D;
input CLK, RSTB;
output [N-1:0] Q;

reg [N-1:0] Q;

always @(posedge CLK or negedge RSTB)
if(!RSTB) Q <= 0;
else Q <= D;
endmodule // DFF

Since D flip-flop is a sequential logic, and inside the
sensitivity list should have "posedge CLK" & "negedge RSTB".

NOT only CLK or RSTB, which will be synthesized into the
combinational logic !

I don't understand why XHDL translate in this way.
(Maybe I should follow some rules to get the desired result ?)

Any suggestion ?

x-HDL problem

I had used X-HDL. But now I have not used it. I think X-HDL can not trasfer correct verilog RTL code. It has many problem. The codes that comes from X-HDL, should be changed by manual. I think it is not proper tools for VHDL2Verilog or Verilog2VHDL.

Try an other tool as well and compare the results .

use formal verification to double-check

We usually use Formality from Synopsys to check the converted code. You will be surprised how many problems Formality can catch. The miscompare is usually caused by some lousiness in the source RTL. By cleaning up the source RTL, we can usually get better results. Also, the source RTL is usually higher level, not the RTL of a primitive DFF as shown in the example. It usually works out OK.

It seems that X-HDL can do VHDL2VER better than the other way. Probably because VHDL is more strictly structured.


1. make sure "synopsys synthsizable " option on . (Very important)
2. put your clock process vhdl sensitivity list only contain clk and reset (verilog like)
3. make sure to convert the whole rtl codes from bottom to top level
4. dont think to convert completely vhdl test bench to verilog like rtl
if you know only vhdl and must do this,
dont assign value when claim one signal ,
dont asign signal value when the signal behavior as one connection wire ,
dont use the utility package or external package ,
use procedure to write the subprogram ,
use process to write test bench like a rtl code .

i used x-hdl many years , convert thousands of vhdl codes/ip to verilog .
it really help me a lot to focus on verilog only and prevent the overhead to know the "2nd foregner" lanuage . You will master it if you know more how to control it .

Assume Code is Synthesizable

Thanks for Nobody's experience.

After I select the Assume Code is Synthesizable option,
the translation result is the desired one !
Verilog/VHDL translators for you...
ref: h**p://www.eda.0rg/comp.lang.vhdl/FAQ3.html#free_translator

(1) Free VHDL to Verilog RTL translator

(2) Commercial Verilog <-> VHDL Translators

1. Alternative System Concepts, Inc.
verilog2vhdl: translates Verilog HDL to VHDL
HDL2verilog: translates VHDL to Verilog HDL.

2. FTL Systems, Inc.
HDL Exchange: convert SPICE to VHDL-AMS or transfer between Verilog and VHDL.

3. X-Tek Engineering
X-HDL: Verilog <=> VHDL Translator, X-HDL
>>> Free to students and universities <<<

The following seems nonexistence now...

4. Avant! Corporation
*** Avant! now is part of Synopsys ***

5. interHDL, Inc.
V to VH: Verilog to VHDL translator.
V to VL: VHDL to Verilog translator.
V to VV: Bi-directional Verilog and VHDL translator.
*** Acquired by Avant? ???

6. Interra, Inc.
VHDL-Bridge: translates Verilog to VHDL

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