xtcx
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What does this mean
This is a code which I'm reviewing for SRIO in Xilinx.
TREQ_SRC_ID and TREQ_ADDR are all inputs to this module with widths of 8-bits and 12bits resp.
I have not used or heard this type of declarations before in VHDL. what is that "right downto 0" as well as "range" keyword doing here?.
Interesting to know, if anybody knows this better, please share briefly.
Code:
signal treq_addr_reg : std_logic_vector(TREQ_ADDR'right downto 0);
signal treq_src_id_reg : std_logic_vector(TREQ_SRC_ID'range);
This is a code which I'm reviewing for SRIO in Xilinx.
TREQ_SRC_ID and TREQ_ADDR are all inputs to this module with widths of 8-bits and 12bits resp.
I have not used or heard this type of declarations before in VHDL. what is that "right downto 0" as well as "range" keyword doing here?.
Interesting to know, if anybody knows this better, please share briefly.