std_logic_vector(xxx'right downto 0) in VHDL, anyone hav any idea?...

[xtcx]

What does this mean

signal treq_addr_reg        : std_logic_vector(TREQ_ADDR'right downto 0);
signal treq_src_id_reg      : std_logic_vector(TREQ_SRC_ID'range);

This is a code which I'm reviewing for SRIO in Xilinx.
TREQ_SRC_ID and TREQ_ADDR are all inputs to this module with widths of 8-bits and 12bits resp.
I have not used or heard this type of declarations before in VHDL. what is that "right downto 0" as well as "range" keyword doing here?.
Interesting to know, if anybody knows this better, please share briefly.

 

[TrickyDicky]

these are attributes. These attributes exist for all types (well the range is for arrays)

so consider the following arrays:

signal a : std_logic_vector(7 downto 0);
signal b : std_logic_vector(0 to 7);

a'range = 7 downto 0
b'range = 0 to 7

a'length = 8
b'length = 8

a'high = 7
b'high = 7

a'low = 0
b'low = 0

a'left = 7
b'left = 0

a'right = 0
b'right = 7

---------- Post added at 13:40 ---------- Previous post was at 13:39 ----------

See here for a list of attributes: VHDL Predefined Attributes

 

[xtcx]

these are attributes. These attributes exist for all types (well the range is for arrays)

so consider the following arrays:

signal a : std_logic_vector(7 downto 0);
signal b : std_logic_vector(0 to 7);

a'range = 7 downto 0
b'range = 0 to 7

a'length = 8
b'length = 8

a'high = 7
b'high = 7

a'low = 0
b'low = 0

a'left = 7
b'left = 0

a'right = 0
b'right = 7

---------- Post added at 13:40 ---------- Previous post was at 13:39 ----------

See here for a list of attributes: VHDL Predefined Attributes

Oh...great information.
Thanks Dude.
Just one more...,
so consider if suppose the input reg "TREQ_ADDR" is of the following type comes with

entity(
TREQ_ADDR : IN std_logic_vector(0 to 33);

In this case, what will be the value of then following signal if declared with this attribute?.

signal TREQ_ADDR_t    : std_logic_vector(TREQ_ADDR'right downto 0)

it will become std_logic(33 downto 0)?...right?.

The Xilinx SRIO IP prrovides TREQ_ADDR a std_logic_vector(0 to 33) (Dont know why,Because of LE format?).

Q1: In the code, they have used this right' attribute to select the width. The output of IP is fixed width (34 bits). But then why is such methodology used?, is this to only enhance coding style?, or does it have any advantage?.

Q2: What's the direct usage of (0 to 33), instead of (33 downto 0), can I consider (0 to 33) as little endian format?.
Thanks...

 

[TrickyDicky]

I can only assume they have declared it like that because of documentation. I have no knwoledge if the SRIO IP, but I know for other things (like Power PCs) have their MSBs where you would normally expect the LSBs on the address bus (so address bit 32 is actually byte select), so yes, it is a way to get around this kind of annoying problem.

Of course, the problem with this method is, if TREQ_ADDR is declared (33 downto 0), then TREQ_ADDR_t becomes (0 downto 0), which Im sure would cause all sorts of problems. It probably would have been better/safer if Xilinx had used the 'reverse_range attribute, which is clearly what they're trying to do.

How you use them is up to you. Most people like to stick to just one, generally downto, as this how numbers are usually written. (powers of 2 increasing as you move to the left).
A common usage of to is for arrays of registers or memorys, because direction doesnt really matter here. eg:

type mem_t is array(0 to 255) of std_logic_vector(7 downto 0);

I personally also use to if its a shift register, just so I know its not a number (it also maps a bit easier if you were to draw it on paper, so 0, the LSB, or first shift stage, is on the left of the diagram, and left of the declaration).

just a little gotcha. constant arrays that are not given an explicit direction, will default to "to"
constant some_SLV : std_logic_vector := "00011110";

 

[xtcx]

Good explanation Dude
Just recently found in Microblaze of xilinx soft-processor, there too they have seemed to have followed the same method of "to" instead of "downto". Because of the reverse nature, the right attribute just worked. I now understood that this is done purely for the compatibility of the code since "downto" is followed everywhere in my prj RTL code, but the IP was just using SLV "to". That makes the confusion.

But to my point, they knew the bit width of the input TREG_ADDR is gonna be 34-bit which is std for SRIO, and why bother writing

TREG_ADDR_t    : std_logic_vector(TREG_ADDR'right downto 0)?

...instead as simply could've written as

TREG_ADDR_t    : std_logic_vector(33 downto 0);

then I wouldn't have been confused :lol:

Thanks Bro...

 

[std_match]

can I consider (0 to 33) as little endian format?.

No, it's the other way around. (0 to 33) is big endian.
(33 downto 0) is little endian.

I think it is better to do the declaration like this:

signal TREQ_ADDR_t    : std_logic_vector(TREQ_ADDR'length-1 downto 0)

It will work regardless of the direction of TREQ_ADDR.

I prefer little endian. For example, if you want to check if a number is odd, just look at bit zero!
What bit should you look at in a big-endian system?

 

[xtcx]

Must be bit 31, quite the oppsosite.
okay,
(33 downto 0) represents MSB bit (33) is at higher position which is what I remember Big-endian, is it not so?

 

[std_match]

Must be bit 31, quite the oppsosite.
okay,
(33 downto 0) represents MSB bit (33) is at higher position which is what I remember Big-endian, is it not so?

That is the problem with big-endian. A certain bit has a an index that depends on the data width.

With little endian, you always know what bit zero is.
With big endian, the bit index says nothing unless you make a calculation that involves the data width.

It has been common with mixed big/little endian systems.
If you look at old Motorola processors, the bit numbering is little endian, but the byte addressing is big-endian (how the bytes are placed in larger words).

 

[xtcx]

If I maintain (33 downto 0) all throughout the code, can we say my design is little endian?....
or if (0 TO 33) can I call as big endian ?

I also know there is no endian thing in SLV. Also the endian comes onyl when packing bytes to a memory(which LSB\MSB to store first),


If I declare (33 downto 0) and if I start sending Left'most bit out then, it is MSB first. So this is ______ endian?

lly if I delcare(0 to 33), then if I start sending Left'most bit out, it is LSB first. so this is _____endian?

 

[TrickyDicky]

I think the way a vector is declares is mearly for your peace of mind/sanity, rather than explicit endianness.

---------- Post added at 11:16 ---------- Previous post was at 11:12 ----------

PS. What will drive you mad, is when the bytes are arranged

0 1 2 3 etc

but individual bits are arranged

7 6 5 4 3 2 1 0

Then neither to or downto will help you write a 32 bit word! (like file systems!)

 

[xtcx]

Thanks...Dude