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Static timing analysis

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gaurp

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How to completely explain interviewer about STA ? i have been using master slave flip and explaining the stuff from very basic with definitions to setup and hold time. but a pure guidance and expected answer would be great .
Additionally For all the STMicro guys , how should i approach to an interview in digital domain bieng a fresher. :roll:
 

ThisIsNotSam

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if you go into a synthesis interview and start talking about flip flop architecture I can assure you that you will be perceived as naive. all flip-flops are master slave DFFs, no one uses anything else. you can appear to be wiser if you talk about corners, process variation, physical estimation, etc., all these complex elements that make synthesis much harder today than it was 20 years ago.
 
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    gaurp

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gaurp

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Static Timing Analysis

Let us say we have a launch capture flip flops working on same clock and same edge.
Now if setup is critical , and there is hold violation how can we optimize it so that no violation occur
PS : I dont think there is any way except changing libraries , and using lvt cells/ hvt cells.
 

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I don't understand your example. Hold violations are fixed by adding delay. In some cases, you sacrifice setup to fix hold. That's a very common trade-off.
 

swabhi812

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Re: Static Timing Analysis

Let us say we have a launch capture flip flops working on same clock and same edge.
Now if setup is critical , and there is hold violation how can we optimize it so that no violation occur
PS : I dont think there is any way except changing libraries , and using lvt cells/ hvt cells.

Generally if you have a setup violation on a given path, you do not have hold violation on same path. You can probably have hold violation on some other fanin cone of endpoint which you can fix by adding buffers. Using lvt and hvt cells is a common practice. I am not sure what you are trying to ask here. Please ask specific questions with some realistic paths.
 

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