Static timing analysis is used to verify the delays within the design. Using STA, you should verify every path and detect serious problems such as glitches on the clock, violated setup and hold times, slow paths, and excessive clock skew.
Dynamic timing simulation is used for timing analysis of asynchronous designs as well as synchronous designs. Using dynamic simulation the verification can be done to verify the functionality as well as the timing requirements of a design. But it needs to develop comprehensive input vectors to check the timing characteristics of critical paths in a design.