This is the state machine I have to build for my project. View attachment Project4.pdf. This is my program thus far. It has no errors, but I don't know how to write the output correctly. Also I don't know how to write a testbench. Could someone give me some ideas. I'm stuck. It has took me quit a while to get this far. Im new at vhdl.
libraryIEEE;useIEEE.STD_LOGIC_1164.ALL;-- Uncomment the following library declaration if using-- arithmetic functions with Signed or Unsigned values--use IEEE.NUMERIC_STD.ALL;-- Uncomment the following library declaration if instantiating-- any Xilinx primitives in this code.--library UNISIM;--use UNISIM.VComponents.all;entity project4a isPort(Clock:inSTD_LOGIC;
Resetn :inSTD_LOGIC;
R :inSTD_LOGIC;
S :inSTD_LOGIC;
T :inSTD_LOGIC;
Z :outSTD_LOGIC);end project4a;architecture Behavioral of project4a istype state_type is(A, B, C, D);signal y : State_type;beginProcess(Resetn, clock)beginIf resetn = '0' then y <= A;ElsIf(clock' Event andClock= '1')ThenCase y iswhen A =>If(s = '1' and T = '1')then y <= A;elsIf(s = '1' and T = '0')then y <= B;elsIf s = '0' then y <= C;EndIf;when B =>If R = '0' then y <= B;ElsIf R='1' then y <= C;endif;when c =>If(R='0' and T='0')then y<=B;elsif(R='1' and T='1')then y<=B;elsif(R='1' and T='0')then y<=A;elsif(R='0' and T='1')then y<=D;endif;when D=>If R='0' then y<=A;else y<=D;endif;endcase;endif;endprocess;
z<= '1' when(y = C or y = d )Else '0';--This is not correct just here to see if the program will work.
Without any scope of what you're supposed to be doing, its difficult to give you any pointers. As for the testbench, there are plenty of tutorials out there, so get googling.
The outputs are the same as the D Flip Flops inputs.
For example A = 1000 ; output = 1000
B = 0100 ; output = 0100
C = 0010 ; output = 0010
D = 0001 ; output = 0001
Yes you are correct D loops back to A unconditionally. I am still having trouble with the test bench. I finally finished the one-hot encoding table. Once I build it in excel I will post it to let you see maybe one of you guys can me some ideas on the test bench. I looked online for test benches but I cant make any since of them.
Once I build it in excel I will post it to let you see maybe one of you guys can me some ideas on the test bench. I looked online for test benches but I cant make any since of them.
The testbench to test the FSM is just driving a value to all the inputs in the FSM design (your entity ports) according to all sequence of transitions as in the state machine diagram. that's all.