State Machine issues! Output and Testbench!

[Bobbyunccstudent]

This is the state machine I have to build for my project. View attachment Project4.pdf. This is my program thus far. It has no errors, but I don't know how to write the output correctly. Also I don't know how to write a testbench. Could someone give me some ideas. I'm stuck. It has took me quit a while to get this far. Im new at vhdl.

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Code VHDL - [expand]
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
 
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity project4a is
    Port ( Clock : in  STD_LOGIC;
           Resetn : in  STD_LOGIC;
           R : in  STD_LOGIC;
           S : in  STD_LOGIC;
           T : in  STD_LOGIC;
           Z : out  STD_LOGIC);
end project4a;
 
architecture Behavioral of project4a is
type state_type is (A, B, C, D);
signal y : State_type;
 
begin
 
Process (Resetn, clock )
begin
If resetn = '0' then y <= A;
ElsIf ( clock' Event and Clock = '1') Then
Case y is
when A => 
If (s = '1' and T = '1') then y <= A;
elsIf (s = '1' and T = '0') then y <= B;
elsIf s = '0' then y <= C;
End If;
 
when B => 
If R = '0' then y <= B;
ElsIf R='1' then y <= C; 
end if;
 
when c => 
If (R='0' and T='0') then y<=B;
elsif (R='1' and T='1') then y<=B;
elsif (R='1' and T='0') then y<=A;
elsif (R='0' and T='1') then y<=D; end if;
when D=>
If R='0' then y<=A;
else y<=D; end if;
end case;
end if;
end process;
z<= '1' when (y = C or y = d ) Else '0'; --This is not correct just here to see if the program will work.

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[Pradeepbp]

when D=>
If R='0' then y<=A;
else y<=D; end if;

From your state machine diagram, when D , shouldn't it branch to A unconditionally??

 

[TrickyDicky]

Without any scope of what you're supposed to be doing, its difficult to give you any pointers. As for the testbench, there are plenty of tutorials out there, so get googling.

 

[Bobbyunccstudent]

From your state machine diagram, when D , shouldn't it branch to A unconditionally??

D goes back to A when the S input goes low, otherwise it stays at D.

 

[soloktanjung]

when D=>
If R='0' then y<=A;
else y<=D; end if;

From your state machine diagram, when D , shouldn't it branch to A unconditionally??

I agree.

From the state diagram, I do not see any outputs.

 

[Bobbyunccstudent]

I agree.

From the state diagram, I do not see any outputs.

The outputs are the same as the D Flip Flops inputs.
For example A = 1000 ; output = 1000
B = 0100 ; output = 0100
C = 0010 ; output = 0010
D = 0001 ; output = 0001

Yes you are correct D loops back to A unconditionally. I am still having trouble with the test bench. I finally finished the one-hot encoding table. Once I build it in excel I will post it to let you see maybe one of you guys can me some ideas on the test bench. I looked online for test benches but I cant make any since of them.

Thanks

 

[soloktanjung]

Once I build it in excel I will post it to let you see maybe one of you guys can me some ideas on the test bench. I looked online for test benches but I cant make any since of them.

Thanks

The testbench to test the FSM is just driving a value to all the inputs in the FSM design (your entity ports) according to all sequence of transitions as in the state machine diagram. that's all.