state encoding for FSM and synthesis

[sun_ray]

Suppose in the rtl of the FSM one encoding style is provided for states. Suppose during the synthesis of the same RTL using Design compiler the state encoding style was chosen by Design compiler command, different than the encoding style of states in the rtl.

Regards

 

[dave_59]

And your question is?

 

[sun_ray]

And your question is?

Sorry the questions is:

What encoding will the synthesis tool take then during synthesis, the rtl encoding of the fsm as in the rtl or the encoding style that was provided to the Design compiler for fsm encoding?

Regards

 

[sharath666]

It should take the encoding info provided to DC..

 

[sun_ray]

It should take the encoding info provided to DC..

Why? Why will not take the state encoding in rtl?

Have you ever provided state encoding in DC for synthesis? What is the default state encoding in DC? Will the default state encoding in DC even have priority over the rtl encoding?

 

[rca]

do you want to encode with a one-hot state machine?
if yes, the synthesis tool has some attribute to preserve this, or some pragma to be added in the code at the variable declaration.

 

[sun_ray]

rca

Our question is different. We asked what will happen when encoding is provided both in rtl and also to DC too as described by you.

Regards