rahdirs
Advanced Member level 1
Hi,
The subject title of this question came out a bit weird,so i'm going to explain my query -
From UART i'm driving a 32 bit register(write_high).The register is the number of clock cycles i want to keep wr_en of FIFO high.
So if that register was x"0000000F" - then wr_en needs to be high for 15 clk cycles.
I was thinking of writing something simple like :
But the above snippet will not do as the count can't be brought back to 0 after counting for write_high number of cycles as it will again keep counting for those cycles if we bring it to 0.
The subject title of this question came out a bit weird,so i'm going to explain my query -
From UART i'm driving a 32 bit register(write_high).The register is the number of clock cycles i want to keep wr_en of FIFO high.
So if that register was x"0000000F" - then wr_en needs to be high for 15 clk cycles.
I was thinking of writing something simple like :
Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 signal count : std_logic_vector(31 downto 0) := x"00000000"; -- --write high is the register into which UART will write number of pulses to store begin process(clk) if (write_high /= x"00000000") then fifo_wr_en <= '1'; if (count = write_high) then fifo_wr_en <= '0'; -- count <= x"00000000" else count <= count + '1'; end if; else fifo_wr_en <= '0'; end if; end process;
But the above snippet will not do as the count can't be brought back to 0 after counting for write_high number of cycles as it will again keep counting for those cycles if we bring it to 0.
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