Start conition detection on serial transmission

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cocopa

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Hi! I have two FPGAs that communicate through only 2 signal lines (clock and data line) and the communication protocol will be based on packets of 16 bits (custom protocol, not I2c). My question is, how can the slave detect the start condition of the packet? What techniques are there to recognize when the packet begins? Thank you.
 

You can try out a 'rs232-like'way: Keep the line in a high state, and before you send a packet, use a start bit, with value zero. Same goes for end bit.
 
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    cocopa

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Thank you very much! I forgot to mention that these are LVDS signals and i'm using Spartan 6LX9, is it possible to detect high state in LVDS? I'm a newbie in FPGAs so my questions may be stupid..
 

maybe you could have a look at manchester coding/decoding?
 

cocopa said:
Thank you very much! I forgot to mention that these are LVDS signals and i'm using Spartan 6LX9, is it possible to detect high state in LVDS? I'm a newbie in FPGAs so my questions may be stupid..
Click to expand...

LVDS and CMOS wont make much difference here. when you translate inside FPGA it will be the same, but I think,
LVDS negative input will give you inverted logic, ie., '0' if input is supposed to be '1', so you gotta be cautious when using it....
Click to expand...

Someone Correct me if wrong....:roll:
 

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