standard cell characterization problem

[kkkhunter]

standard cell characterization

Now I have difficulty in setup and hold time calculation in standard cell characterizing definition. I need to compare the sequential cell delay step by step so I wish I can have program calculation in Hspice like 'for...if..'.

Or I have to use the bisection command in spice? I feel the bisection command has some problem or conflicts on the setup and hold characterization.

Anyone have the experience or some reference? Please help me. Thanks.

 

[tomorrowglue]

standard cell characterization + hspice

Cadence has a library characterization tool (called ELC), which can run spice. It does not use bisec command in spice to characterize setup/hold time as far as I know. Probably you can try writing a script to run spice and use bisec algorithm.

 

[nav_vlsi]

cell characterization definition

This is how a sample hspice template from bisection algorithm looks like, i was using it to measure setup time.

please note that u need to select the window size properly to get accurate results.

Nav

------- Sample Template -------
* DFF_top Bisection Search for Setup Time
.lib '/path of models/model.lib' corner_type
.include 'Extracted ckt netlist'
.PARAM DelayTime= Opt1 ( 0.0n, 0.0n, 4n )

.TRAN 0.1n 4n Sweep
+ Optimize = Opt1
+ Result = MaxVout
+ Model = OptMod
.MEASURE Tran MaxVout Max v(Q) Goal = `v(VDD)'
.MEASURE Tran SetupTime Trig v(D) Val = `v(VDD)/2' Fall = 1
+ Targ v(CK) Val = `v(VDD)/2' Rise = 1
.MODEL OptMod Opt
+ Method = PASSFAIL
.OPTIONS OPTLST = 1

.global vdd vss vsub
.temp 125
.param vss=0 vsub=0 vdd=1.0v
VVSS VSS 0 0
VVDD VDD 0 vdd
vd D 0 PWL (0ns vdd 1ns vdd 1.15ns vss Td = "DelayTime")
vck CK 0 PWL (0ns vss 3ns vss 3.15ns vdd)
cca Q 0 10f
ccb QN 0 10f
XFLIPFLLOP_NAME VDD VSS Q QN CK D FLIPFLLOP_NAME
.end
---------------------------------

 

[kkkhunter]

standard cell characterization

Thanks for all your help.
I knew the bisection algorithm in hspice. But I think the setup time value calculated by bisection is not a well-exact value. Nowadays, the setup time is defined as follow, there is a typical D-Q delay with an infinite setup time, the expected setup time will make the D-Q delay larger than the typical delay for 10 or 30 percent. Well in bisection algorithm, the setup time judgement is pass or fail. So its precision is poor.
So I think the bisection algorithm is not suitable in standard cell characterizing definition.

 

[eklikeroomys]

Halo,

How can I obtain the SPICE files required by the ELC tool for the characterisation of a new standard cell library?

Thank you

 

[nitin kala]

Re: standard cell characterization

Thanks for all your help.
there is a typical D-Q delay with an infinite setup time, the expected setup time will make the D-Q delay larger than the typical delay for 10 or 30 percent..

its Ck-Q delay..not D-Q delay

- - - Updated - - -

you have to extract SPICE file from the layout for new standard cell characterization

 

[bharatesh7]

Re: standard cell characterization

its Ck-Q delay..not D-Q delay

- - - Updated - - -

you have to extract SPICE file from the layout for new standard cell characterization

Hi,
can you please explain me what is delay_degradation is 10% means. "actually when the clock2 Q delay reaches max delay_degradation of 10%,then we end up with the result" is This means when Clock to Q delay starts increasing at max time specified by delay_degradation...is that time the simulation will stop..?????

 

[nitin kala]

Re: standard cell characterization

first you measure clk-Q reference delay by giving D input at negedge. now you start to vary the D input time wrt clk posdge ( from -5ns to +5ns) point where clk-Q delay exceeds 10% of the reference delay calculated before is the point where simulation is stopped. clk time - this time = setup time.

Thanks,
Nitin

 

[bharatesh7]

Re: standard cell characterization

first you measure clk-Q reference delay by giving D input at negedge. now you start to vary the D input time wrt clk posdge ( from -5ns to +5ns) point where clk-Q delay exceeds 10% of the reference delay calculated before is the point where simulation is stopped. clk time - this time = setup time.

Thanks,
Nitin

How you will measure the reference delay...?? at what time point you start..?? and is it -5ns to +5ns means around the clock pos edge (before pos edge of clock and after pos edge of clock) ...???

 

[nitin kala]

Re: standard cell characterization

you can measure reference delay by giving input at previous negedge.
Yes, +- 5ns is around clock posedge.

 

[Prashanthanilm]

Re: cell characterization definition

Hi,

I need to calculate the floating node in the circuit , which language code is better? Hspice or orther