[STA] set input delay and output delay query

[maulin sheth]

Hello All,

What is the meaning of set_input_delay and set_output_delay?
Suppose I have set input delay max is 14 ns and min is 6ns(calculated on basis of setup,hold, min path delay and max path delay).
If I set input delay -max 14 -min 6ns,
does it mean that data must reach before 14ns? Please help me to understand this.

Is there any possibility to become more worst situation in actual fabricated device thn we have taken during max delay calculation?

Thanks & Regards,
Maulin Sheth

 

[sharath666]

Input delay is the time taken outside the chip for the input signal. If it takes more than the max value there will be a setup violation for the 1st flop in the path.
Usually pessimistic values are considered so I presume after fabrication and board design, it should be fine. I personally have not come across such a situation.

 

[maulin sheth]

Hello,

Thanks for reply.
But I am confused because as you say "f it takes more than the max value there will be a setup violation for the 1st flop in the path".
We are calculating max value using max/worst condition, so it is possible to be more worst condition than what we have calculated?

Thanks & Regards,
Maulin Sheth

 

[sharath666]

But as I have said "Usually pessimistic......". So the "more worst condition" you are talking about will usually not arise.

 

[maulin sheth]

Hello,
Thanks for reply.
As you said "Input delay is the time taken outside the chip for the input signal. If it takes more than the max value there will be a setup violation for the 1st flop in the path"
So if it is usually not arise the condition of more worst case, thn why it may take more than max value?

 

[sharath666]

Actually the chip designer is not aware of the details of the pcb. He assumes a number for the external routing on the board and the trace delay(and other delays which I am not aware of).

 

[maulin sheth]

Yes. That is true that chip designer is not aware of the details of PCB, than how we can take maximum path delay as it is not known? thn we can not set i/o delay for maximum if we have no idea, how the number come?

 

[sharath666]

I am assuming that they take some rough numbers to start off with and then keep improvising. Obviously when a project starts off, all the teams(the board, the chip design,the validation....) work together for some time. They will come up with some numbers during this phase.