STA & PD inter relation

[pavi622]

hi i have some doubts, can any1 plz clarify

1. What is the difference btw RTL & synthesised netlist

2. What are PVT corners & how are thy defined.

3. What is the relationship between PVT corners & delay for a particular library?

 

[soloktanjung]

1. RTL is designs in VHDL or Verilog. Synthesized netlist is produced when the RTL designs is translated to logic/standard cells according to certain technology. Both have similar functionality but different forms.

Thanks

 

[vijayR15]

Hai pavi,

1. As hairo said RTL(Register Transfer Level) which is code in verilog or VHDL(Here u will use some gates ex:-and , nand etc..,) When u synthesized these gates will be replaced with some gates in technology lib)

EX:- Assume your lib has "and gate" as AND1X


then synthesized file .v will consists as

"AND1X A1 (.A (n_335), .B (n_541), .Z (n_336));"

A1 is the instance name.

2. PVT is process, voltage and temperature. The lib file contatin details about it.. They are defined based on working conditions of that corresponding lib cells..

3. By default a lib will have all these three Process, voltage and temp value. So each cell in lib will have a delay value based on pvt.. Thats why we are choosing worst case lib for setup and best case for hold....

 

[vimalraj205]

hai frnds

1. RTL is REGISTER TRANSFER LOGIC which is in the form of behavioural modelling so in order to change this to standard cell format, it is synthesized to convert it in to the gate level modelling corresponding to the standard cells present in the library

2. PVT (Process Voltage Temperature)

in the best case library Voltage is HIGH and Temperature is LOW Process is Fast ----> delay values are low ---> used for Hold analysis

in the worst case library Voltage is LOW and Temperature is HIGH Process is Slow----> delay values are high ---> used for setup analysis