Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

STA and asynchronous reset

Status
Not open for further replies.

sun_ray

Advanced Member level 3
Joined
Oct 3, 2011
Messages
772
Helped
5
Reputation
10
Reaction score
5
Trophy points
1,298
Activity points
6,828
Why it is difficult to handle STA if asynchronous resets are present?
 

jirika

Member level 2
Joined
Apr 19, 2011
Messages
43
Helped
14
Reputation
26
Reaction score
13
Trophy points
1,288
Location
Prague
Activity points
1,478
It isn't difficult if you will use CASE condition.
 

slsindorf

Newbie level 3
Joined
May 15, 2013
Messages
4
Helped
3
Reputation
6
Reaction score
3
Trophy points
1,283
Activity points
1,308
In my experience, when the .lib files are not too weird, there is never any problem with STA and asynchronous resets.
What kind of difficulties do you mean?
 

jt_eaton

Member level 4
Joined
Aug 26, 2012
Messages
72
Helped
20
Reputation
40
Reaction score
19
Trophy points
1,288
Location
Vancouver, Wa USA
Activity points
1,779
Why it is difficult to handle STA if asynchronous resets are present?

The problem occurs when you use a soft reset system with multiple domains. Supose you wanted to put
a block of logic on it's own switched power island. You must use a soft reset to create a reset domain for
that block. To power it off you must first use the soft reset to hold the block in reset. Then you latch the
outputs while blocking the inputs going to the block. Finally you can switch off the power.

Reverse those three steps to restore power.


The problem occurs when the logic in that block uses asynchronous resets. When the soft reset system
asserts reset then it will pass through the flops and change the outputs. Since the rest of the chip is not
going in reset then these are valid timing paths and they will be longer than the usual clk-> Q path.

So Mr component designer choses an asynchronous reset because he doesn't want to see any reset logic
in his D pathways. Well he doesn't see any in his logic but he is putting it in every one of your signals that
routes between different soft reset domains.

Thats why you should never use asynchronous resets in any of your core logic.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top