If you use SRAM generated from a memory compiler, then you can get relatively high speed, at least higher than 10 ns, but still depend on the technology node.
If you code the SRAM in RTL and use in your design, I have dont know.
If you use SRAM generated from a memory compiler, then you can get relatively high speed, at least higher than 10 ns, but still depend on the technology node.
If you code the SRAM in RTL and use in your design, I have dont know.
What I mean is that, if you can get a memory compiler, you can generate SRAM with higher clock speed, meaning that less than 10ns clock period.
You can select the SRAM speed from the memory compiler before generate it timing lib, LEF, etc.
I suppose what u say above is SRAM from memory compiler is faster than code it self.
Are you talking about external SRAM connected to programmable logic (FPGA) or internal block RAM?
The latter is in fact synchronous static RAM (SSRAM) and achieves cycle speeds up to several 100 MHz. With external asynchronous static RAM, it's difficult to achieve high speed. Synchronous static RAM with pipelined command and address processing would be preferred.
Are you talking about external SRAM connected to programmable logic (FPGA) or internal block RAM?
The latter is in fact synchronous static RAM (SSRAM) and achieves cycle speeds up to several 100 MHz. With external asynchronous static RAM, it's difficult to achieve high speed. Synchronous static RAM with pipelined command and address processing would be preferred.