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sram problem in high speed design ??

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lpeter

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I have two option in my design. one is using sram, the other not.

However, the speed of SRAM is limited, about 10ns, i cannot to breakdown the path to increase the clock rate.

For the one not using SRAM, i can always insert some registers to pipeline to increase the speed. Is that mean

in high speed design, we preferred not using SRAM or is there any other solution?
 
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If you use SRAM generated from a memory compiler, then you can get relatively high speed, at least higher than 10 ns, but still depend on the technology node.

If you code the SRAM in RTL and use in your design, I have dont know.

Is the 10 ns delay after the routing?

Thanks.
 

If you use SRAM generated from a memory compiler, then you can get relatively high speed, at least higher than 10 ns, but still depend on the technology node.

If you code the SRAM in RTL and use in your design, I have dont know.

Is the 10 ns delay after the routing?

Thanks.

10ns I think is the measured time per access.

But I think 10ns is a bit slower because processing speed i needed is about 1Gs/s.

I suppose what u say above is SRAM from memory compiler is faster than code it self.

btw, does coding SRAM in RTL only mean code memory controller(memory cell generate auto?) ?

Thanks.
 

I'm sorry for not making it clear.

What I mean is that, if you can get a memory compiler, you can generate SRAM with higher clock speed, meaning that less than 10ns clock period.
You can select the SRAM speed from the memory compiler before generate it timing lib, LEF, etc.

I suppose what u say above is SRAM from memory compiler is faster than code it self.

Yes.

does coding SRAM in RTL only mean code memory controller(memory cell generate auto?)

I mean code the SRAM memory architecture including the controller.

Thanks.
 

sorry, one more question.

How can memory cell be coded in VHDL ? I thought it was physical.

For memory controller, I can understand it can be wrote in vhdl and synthesible.

Thanks.
 

Are you talking about external SRAM connected to programmable logic (FPGA) or internal block RAM?

The latter is in fact synchronous static RAM (SSRAM) and achieves cycle speeds up to several 100 MHz. With external asynchronous static RAM, it's difficult to achieve high speed. Synchronous static RAM with pipelined command and address processing would be preferred.
 

Are you talking about external SRAM connected to programmable logic (FPGA) or internal block RAM?

The latter is in fact synchronous static RAM (SSRAM) and achieves cycle speeds up to several 100 MHz. With external asynchronous static RAM, it's difficult to achieve high speed. Synchronous static RAM with pipelined command and address processing would be preferred.

I am talking SRAM for ASIC.
 

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