Sram during read, regarding bit line

[iamxo]

During read operation, the BL remains VDD (slightly down in simulation), while BL_ decrease or vice versur until the voltage difference is about 100mV (mostly). But what I could not understand is why both the bit line voltage rise to VDD after the access transistor is turned off. It's due to leadage?

Anyone could help me? Thanks in advance..

 

[iamxo]

Anyone help me clarify??

Thanks again.

 

[jbeniston]

Try the analog forum maybe?

 

[iamxo]

I got it.

Another precharge ckt works after the 100mV voltage difference is generated, because the circuit is large I did not notice that at first.

Thanks all.