tiger_shark
Member level 1

cross-talk inside FPGAs?
Hi,
I am involved in a project that uses Xilinx S3-1500. He highest clock is 108 MHz and we observe that the clock will have a whole chunk of spurs on it, specially the 54,27 MHz which are generated inside FPGA using DCMs. My question is , Do you think it might be happening from cross-talk between clock-tree and the logics inside FPGA at this speed?
Any comments on this would be appreciated.
Regards- TS
Hi,
I am involved in a project that uses Xilinx S3-1500. He highest clock is 108 MHz and we observe that the clock will have a whole chunk of spurs on it, specially the 54,27 MHz which are generated inside FPGA using DCMs. My question is , Do you think it might be happening from cross-talk between clock-tree and the logics inside FPGA at this speed?
Any comments on this would be appreciated.
Regards- TS