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Spurs on clock caused by cross-talk inside FPGAs?

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tiger_shark

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cross-talk inside FPGAs?

Hi,

I am involved in a project that uses Xilinx S3-1500. He highest clock is 108 MHz and we observe that the clock will have a whole chunk of spurs on it, specially the 54,27 MHz which are generated inside FPGA using DCMs. My question is , Do you think it might be happening from cross-talk between clock-tree and the logics inside FPGA at this speed?

Any comments on this would be appreciated.
Regards- TS
 

cross-talk inside FPGAs?

That’s a really interesting one.

I have never seen a problem with cross-talk inside the device, would you be kind enough to share you findings on this one TS.

Many Thanks Bob
 

Re: cross-talk inside FPGAs?

I will do so if I fiind anything. I guess the problem should have other causes rather than cross-talk in FPGA. That was one of the possibilities that I have in mind. if I didn't get back to you in a week or so, please remind me again.

Any thought or previous experiences like this from other experts?

Thanks for the help,
Regards - TS
 

Re: cross-talk inside FPGAs?

Hi,

All FPGAs and ASICs are designed to avoid possible crass-talk with appropriated software palcement and routement tools. I think that you cannot expect any cross-talk problems under recomended IC conditions.
 

cross-talk inside FPGAs?

hi TS

The only similar effect I’ve seen (and it was in a digital circuit, but not an fpga) was caused by ground bounce. I didn’t realise what was going on until I started to use a fet probe (a standard probe tended to mask the problem).

Any luck with it so far?

Bob
 

Re: cross-talk inside FPGAs?

Hi,

Thanks for sharing the idea. The bouncing ground exists partially but is not believed to be the major reason (maybe managers don't like to believe b/c they have to change 2000 cards :) ) and now we are pursuing pick-up sources that exist out of FPGA (on the board).

Regards- TS
 

cross-talk inside FPGAs?

What exactlly is a problem, can you please post oscilogramm?

Thanks
 

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