[AVR] Spi bit bang slave code implementation

[firstoption]

Good day to all,

Please I need help on how to write the Clock Code for my Slave device. I understand that only the Master device can generate the clock signal while slave device will listen to the incoming signal however I do not know how to implement this concept in the slave program such that the slave can equally send data to the master. I would be very glad if somebody can help me out. Below are my lines of code for both the Master device and the Slave device.



MASTER DEVICE ATTINY4313

#include <avr/io.h>
#include <util/delay.h>


/* SPI port and pin definitions.*/
 
#define _BV(bit)            (1 << (bit)) 
#define  OUT_REG         PORTB //!<  port output register.
#define  IN_REG             PINB //!<  port input register.
#define  DIR_REG         DDRB //!<  port direction register.
#define  CLOCK_PIN         PINB2 //!<  clock I/O pin.
#define  DATAIN_PIN         PINB1 //!<  data input pin.
#define  DATAOUT_PIN     PINB0 //!<  data output pin.

unsigned char   Transmitt_Receive_Master(unsigned char  data);

void SetClock()
{
 PORTB |= (1 << PINB2);   
}

void ClearClock()
{
 PORTB &= ~(1 << PINB2);  
}

void SetData()
{
 PORTB |= (1 << PINB0);   
}

void ClearData()
{
 PORTB &= ~(1 << PINB0);  
}

void Spi_Master_Init()
{
 // set up SCK/MOSI as output Pins
 
 DIR_REG |= (1<<DATAOUT_PIN) | (1<<CLOCK_PIN);

 DIR_REG &= ~(1<<DATAIN_PIN);  // Data-In (MISO) AS input

}

int main(void)
{
   Spi_Master_Init();
   
    while(1)
    {
        Transmitt_Receive_Master(20);
    }
}

unsigned char   Transmitt_Receive_Master(unsigned char  data)
{
 unsigned char i;
 unsigned char ReceivedValue=0;
 
 
 for (i=0;i<8;i++)

 {
  
  if (data & _BV(i))
  {
   SetData();
   
  }
  else
  {
   ClearData();
  }
  
  data <<= 1;
  // set clock high
  _delay_ms(100);
  
  SetClock();
  
  ReceivedValue <<= 1; //shift left one bit
  
   if (IN_REG & DATAIN_PIN )
   {
    ReceivedValue |= _BV(i);
   }
   else
   {
     ReceivedValue &= ~_BV(i);    
   }
  
         ClearClock();
   
 }

 return   ReceivedValue;
}

SLAVE DEVICE ATTINY 2313

#include <avr/io.h>
#include <util/delay.h>


/* SPI port and pin definitions.*/

#define _BV(bit)            (1 << (bit))
#define  OUT_REG         PORTB //!<  port output register.
#define  IN_REG             PINB //!<  port input register.
#define  DIR_REG         DDRB //!<  port direction register.
#define  CLOCK_PIN         PINB2 //!<  clock I/O pin.
#define  DATAIN_PIN         PINB0 //!<  data input pin.
#define  DATAOUT_PIN     PINB1 //!<  data output pin.

unsigned char  Spi_Slave_Init()

{
 
 DIR_REG |= (1<<DATAOUT_PIN); // Set up MISO as output Pins
    DIR_REG &= ~(1<<CLOCK_PIN);  // Clock-Pin  aS input
 DIR_REG &= ~(1<<DATAIN_PIN);  // Data-In (MOSI) AS input


}

void SetData()
{
 PORTB |= (1 << PINB0);
}

void ClearData()
{
 PORTB &= ~(1 << PINB0);
}


unsigned char   Transmitt_Receive_Slave(unsigned char  data)
{
 unsigned char i;
 unsigned char ReceivedValue=0;
 
 
 for (i=0;i<8;i++)

 {
  
  if (data & _BV(i))
  {
   SetData();
   
  }
  else
  {
   ClearData();
  }
  
  data <<= 1;
  // set clock high
  _delay_ms(100);
  
  ReceivedValue <<= 1; //shift left one bit
  
  if (IN_REG & DATAIN_PIN )
  {
   ReceivedValue |= _BV(i);
  }
  else
  {
   ReceivedValue &= ~_BV(i);
  }
  
 }

 return   ReceivedValue;
}

int main(void)
{
     DDRD =0xFF;
  Spi_Slave_Init();
  
    while(1)
    {
       PORTD = Transmitt_Receive_Slave(40); 
    }
}

Thank you all for the usual support .Best regards.

 

[ARQuattr]

Hi,
Normally the master will send a message or command to the slave to request a response, and it will clock out some arbitrary data during which time the slave replies with the data. For example, the master may send a one-byte command to get a one-byte response. It will clock out the command byte, followed by another byte like 0. The slave sees the command byte and then prepares to reply with a data byte. Because only the master can drive the clock, the slave must be ready to send out the data bits of its reply as the clock pulses come from the master. The 0 data that the master sends is ignored by the slave during that time.