Specific SoC Encounter Flow

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steven852

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So far I have prepared the following files for SoC Encounter:

a LEF file, a netlist file, and a SDC file.

According to the manual (search "SoC Encounter Tutorial" on this forum), I am ready to go with Virtual floor plan. However, I am not sure the detail since the tutorial just outlines the steps. Can someone give me some more detail description or documentation that maps the tutorial?

Thanks in advance.
 

u'll also need a .tlf or a .lib file.
 

SVP design: .v .lib .sdc .lef (io file, toggle file, cts spec)
Power analysis: voltagestorm library file
Extraction: Same lib with voltagestorm
SI: .cdB file (celtic)
GDS: layer map file.
 

U need the follwing input files for soc

.v(verilog netlist)
. lef, .lib, .sdc, .cap(capcitance tabfile), io file
 

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