[SOLVED] Special Mux or what else?

[zorax85]

This is my question...
I have two modules and they share an I/O bus of 16 bits.
The first module, that we can call module A, needs to use all 16 bits in bidirectional mode.
The second module, that we can call module B, needs to use just 8 bits in output mode.

Which is the best solution in order to provide the normal use of the module A, and sometimes, using a bypass for example, enable the module B?

 

[treqer]

Who should manage the activation of outputs?

 

[TrickyDicky]

I would have modules A and B with separate inputs and outputs, and then let a seperate entity handle the Bidirectional bus and who has control of it.

 

[zorax85]

Maybe this scheme can be useful to understanding my question.

 

[TrickyDicky]

I stick with my idea - let A have separate input and output ports.
Then create a bus controller module.

inside an FPGA, internal tri-states are just converted to muxes, which for module A would be like having separate input and output.

 

[zorax85]

I already have three different signals (two from A the separate input and output, and one from B)

now you mean something like that?

process(s,inp)
begin
case s is
when '0' => op <= inp_A and bus_enable <= enable_A;
when others => op <=inp_B and bus_enable <= '1';
end case;
end process;


and then I have to manage the bidir pins?

 

[TrickyDicky]

no, you will need tristates:

op <=      output_A  when sel = output_A
      else output_B  when sel = output_B
      else (others => 'Z');

---------- Post added at 10:19 ---------- Previous post was at 10:18 ----------

plus you need

input_A <= op;

 

[FvM]

Honestly speaking, I don't see any problem involved with the intention of your initial post. Preferably, you would keep the upper bus bits tristated while module B is driving out to minimize switching noise, but it's not strictly required. For an exact answer, please specify the existing control signals.

 

[zorax85]

no, you will need tristates:

op <=      output_A  when sel = output_A
      else output_B  when sel = output_B
      else (others => 'Z');

---------- Post added at 10:19 ---------- Previous post was at 10:18 ----------

plus you need

input_A <= op;

Following your suggestion:

Data_Pin <= Out_A when ((Out_en = '1') and (sel = '1')) else
Out_B when ((Out_en = '1') and (sel = '0')) else
(others => 'Z');

In_A <= Data_Pin; 

It looks OK...isn't it?

 

[TrickyDicky]

That should work.