[SOLVED] Making a MUX-like process but getting errors (VHDL)

[gilm]

Hi all,

I am trying to do the following in a process in VHDL:

---

Code VHDL - [expand]
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process(FAST_CLK)
    begin
     if rising_edge(FAST_CLK) then
        if RESET = '1' then
           AUDIO_OUT_VALID <= '1';
           AUDIO_OUT <= AUDIO_IN;
        else
            case top_state is
            when WAIT_FOR_FRAME_PART =>....
              .
              .
              .
              .

---

In the testbench I set the reset signal to 0 so that I only expect to see the results of the "else" option. But at the beginning of the waveform the results of
AUDIO_OUT_VALID <= '1';
AUDIO_OUT <= AUDIO_IN;
are showing even though RESET = 0 throughout the entire time. I don't see how this can happen. I would be happy to provide more info if needed. Thanks in advance!

 

[FvM]

Most likely, no other assignment to both signals becomes ever active. You don't show the full code.