This is my question...
I have two modules and they share an I/O bus of 16 bits.
The first module, that we can call module A, needs to use all 16 bits in bidirectional mode.
The second module, that we can call module B, needs to use just 8 bits in output mode.
Which is the best solution in order to provide the normal use of the module A, and sometimes, using a bypass for example, enable the module B?
I already have three different signals (two from A the separate input and output, and one from B)
now you mean something like that?
process(s,inp)
begin
case s is
when '0' => op <= inp_A and bus_enable <= enable_A;
when others => op <=inp_B and bus_enable <= '1';
end case;
end process;
Honestly speaking, I don't see any problem involved with the intention of your initial post. Preferably, you would keep the upper bus bits tristated while module B is driving out to minimize switching noise, but it's not strictly required. For an exact answer, please specify the existing control signals.