deepu_s_s
Full Member level 5
Hello Friends,
I am designing a 9 bit - 10 bit adder. This is a carry look ahead adder. I did that one using for loop. Now I thought the for loop in the design is a bit expensive, so i decided to remodel the design..
I place every variable that is going to be changed in the ALWAYS sensitivity list. So to get the output, it takes 10 cycles.
I didn't included the clock, so that it would be purely combinational. I included the reset to set some initial values. But the non reset block is not executing, can anyone rectify the problem? I need it very urgently
`timescale 1ns / 1ps
module adder(operand1,operand2,reset,sum);
input [8:0]operand1,operand2;
input reset;
output [9:0]sum;
reg [9:0]sum;
reg [8:0]g,p;
reg [9:0]carry;
reg [8:0]temp_sum;
reg overflow;
//wire temp;
integer i;
always @(operand1 or operand2 or posedge reset or g or p or i or carry or temp_sum or i or overflow)
begin
if(reset)
begin
carry = 10'b0000000000;
i=0;
g=9'b000000000;
p=9'b000000000;
temp_sum = 9'b000000000;
end
else
begin
if(i<=8)
begin
g = operand1 & operand2;
p = operand1 ^ operand2;
carry[i+1] = (p & carry)| g;
temp_sum = (p ^ carry);
i=i+1;
end
else
begin
overflow = carry[9] ^ carry[8];
sum=(overflow ==1'b1)?{operand1[8],temp_sum}:{temp_sum[8],temp_sum};
end
end
end
endmodule
thanks and regards
Deepak
I am designing a 9 bit - 10 bit adder. This is a carry look ahead adder. I did that one using for loop. Now I thought the for loop in the design is a bit expensive, so i decided to remodel the design..
I place every variable that is going to be changed in the ALWAYS sensitivity list. So to get the output, it takes 10 cycles.
I didn't included the clock, so that it would be purely combinational. I included the reset to set some initial values. But the non reset block is not executing, can anyone rectify the problem? I need it very urgently
`timescale 1ns / 1ps
module adder(operand1,operand2,reset,sum);
input [8:0]operand1,operand2;
input reset;
output [9:0]sum;
reg [9:0]sum;
reg [8:0]g,p;
reg [9:0]carry;
reg [8:0]temp_sum;
reg overflow;
//wire temp;
integer i;
always @(operand1 or operand2 or posedge reset or g or p or i or carry or temp_sum or i or overflow)
begin
if(reset)
begin
carry = 10'b0000000000;
i=0;
g=9'b000000000;
p=9'b000000000;
temp_sum = 9'b000000000;
end
else
begin
if(i<=8)
begin
g = operand1 & operand2;
p = operand1 ^ operand2;
carry[i+1] = (p & carry)| g;
temp_sum = (p ^ carry);
i=i+1;
end
else
begin
overflow = carry[9] ^ carry[8];
sum=(overflow ==1'b1)?{operand1[8],temp_sum}:{temp_sum[8],temp_sum};
end
end
end
endmodule
thanks and regards
Deepak