module adder(operand1,operand2,
//reset,
sum);
input [8:0]operand1,operand2;
//input reset;
output [9:0]sum;
reg [9:0]sum;
reg [8:0]g,p;
reg [9:0]carry;
reg [8:0]temp_sum;
reg overflow;
//wire temp;
integer i;
always @(*)
begin
for ( i =0; i<9; i = i+1)
begin
g[i] = operand1[i] & operand2[i];
p[i] = operand1[i] ^ operand2[i];
carry[i+1] = (p[i] & carry[i])| g[i];
temp_sum[i] = (p[i] ^ carry[i]);
end
overflow = carry[9] ^ carry[8];
sum=(overflow ==1'b1)?{operand1[8],temp_sum}:{temp_sum[8],temp_sum};
end
endmodule