Somethinng wrong with my code

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deepu_s_s

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Hello Friends,

I am designing a 9 bit - 10 bit adder. This is a carry look ahead adder. I did that one using for loop. Now I thought the for loop in the design is a bit expensive, so i decided to remodel the design..

I place every variable that is going to be changed in the ALWAYS sensitivity list. So to get the output, it takes 10 cycles.

I didn't included the clock, so that it would be purely combinational. I included the reset to set some initial values. But the non reset block is not executing, can anyone rectify the problem? I need it very urgently




`timescale 1ns / 1ps

module adder(operand1,operand2,reset,sum);

input [8:0]operand1,operand2;
input reset;

output [9:0]sum;
reg [9:0]sum;

reg [8:0]g,p;
reg [9:0]carry;
reg [8:0]temp_sum;

reg overflow;
//wire temp;

integer i;



always @(operand1 or operand2 or posedge reset or g or p or i or carry or temp_sum or i or overflow)
begin
if(reset)
begin
carry = 10'b0000000000;
i=0;
g=9'b000000000;

p=9'b000000000;

temp_sum = 9'b000000000;

end
else
begin
if(i<=8)
begin
g = operand1 & operand2;
p = operand1 ^ operand2;

carry[i+1] = (p & carry)| g;
temp_sum = (p ^ carry);

i=i+1;
end
else
begin
overflow = carry[9] ^ carry[8];
sum=(overflow ==1'b1)?{operand1[8],temp_sum}:{temp_sum[8],temp_sum};
end
end
end



endmodule



thanks and regards
Deepak
 

Please go back to the for loop design, it may have a chance. With this one, you're stuck in a dead end.

Or start with an adder example from a textbook.
 

whats wrong with the above code? y the always block is not executing?

The Loop design is giving better results

Thanks and Regards
Deepak
 

Is the non-reset part not running at all or the result is chaos? I meant the result looked like noise? or the output inaccurate?
 

Hi,i think there are some errors in ur code,like syntax error,not-good coding style.
deepu_s_s said:
always @(operand1 or operand2 or posedge reset or g or p or i or carry or
Deepak
Mixed single and double-edge expressions are not supported.
What's more,the variable 'i' does not work as you wish.
Only combinational logic can't implements your function in this way,a CLK is needed.
Hope i helped.

Regards.
 

deepu_s_s said:
whats wrong with the above code?
many things ...

if you really need a pure combo logic try such version:
Code:
module adder(operand1,operand2,
             //reset,
             sum); 

input [8:0]operand1,operand2; 
//input reset; 

output [9:0]sum; 
reg    [9:0]sum; 

reg [8:0]g,p; 
reg [9:0]carry; 
reg [8:0]temp_sum; 

reg overflow; 
//wire temp; 

integer i; 

always @(*) 
 begin 
       for ( i =0; i<9; i = i+1)
       begin 
        g[i] = operand1[i] & operand2[i]; 
        p[i] = operand1[i] ^ operand2[i]; 

        carry[i+1]  = (p[i] & carry[i])| g[i]; 
        temp_sum[i] = (p[i] ^ carry[i]); 
      end 
   overflow = carry[9] ^ carry[8]; 
   sum=(overflow ==1'b1)?{operand1[8],temp_sum}:{temp_sum[8],temp_sum}; 
 end 

endmodule
good luck
 

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