something about synthesis

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chibijia

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recently,i am learning some eda practical class,involves some software,such as design compile,i use it to synthesis my codes,take div_3freq as example!because it involves multi-clock,when meeted this question,how to handle it!
help;help;help;
and i could not view my frequency_divider wave!
what problem i have!
 

As your design consists of more than one clock, your design also consists of clock domain crossing signals.

Please confirm that you have properly used synchronizers and for the CDC signals and followed all CDC rules.

You check this first and then let me know.

--
Regards,
Nirav Bhatt

Added after 4 minutes:

If you don't have any IDEA about CDC, please download below given pdf and get familiar about CDC.
 

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