Some questions about using DC for ASIC design?

[atuo]

optimize_registers

1.how to set constraint on reset signal. I use 'set_ideal_network',and is it right?

2.how to set_max_fanout except clock and reset.

3.When I synthesis a module A the timing slack is small,but I put the module A into a top_level module B and sythesis the top_level module B,and the timing slack is very big. The inputs and outputs port of module A are all rigister,and I don't know why the two result are so different?

 

[horzonbluz]

balance_registers

1. set_drive 0 (reset signal);
set_ideal_networks (reset signal);
OR
set_dont_touch_networks (reset signal);
2. set_max_fanout 1 [input ports];
set_fanout_load 8 [outputs signals];
set_port_fanout_number 4 [outputs signals];
set_max_fanout 8 [current design];
3. I think your constrains that setting on input and output ports are not according to the practical conditions. Please check these constrains carefully.

 

[atuo]

set_ideal_network

hi,horzonbluz

I will check my constraint more carefully.
And have you used constraint:balance_registers or optimize_registers? I read sold but don't know the different of them. I design a pipeline,and meet the timing slack. When I try to optimize the timing. Using the balance_registers after sythesis and DC reports : can't move register. Using the optimize_registers and DC reports:the input delay is too small.
How can I do?


regards
atuo

 

[horzonbluz]

set optimize_registers

1.balance_registers
. Ignore clock period goal and timing slack
. Use "min-period retiming" algorithm In DC synthesis
. Does not minimize area
2. optimize_registers
. Min-period retiming( same as balance_registers)
. Takes advantage of positive slack to reposition registers
at low fanout nodes to reduce total number of registers.
So it can minimize area of design.
Usually we do not use the two commands to optimize our design, because we need to preserve hierachical of our desing. The two commands can flat our design. That is not the result what we want.

 

[atuo]

set_max_fanout

hi,horzonbluz

Thanks for your help.
I use the constraint you provide, and the result of synthesis is good.But I want to know how to decide the num of fanout_load and max_fanout. Is it a convention or not?
BTW my design is a pipeline module.And a stage of the pipeline is critical path. Because I don't want to modify my RTL, I have to depend on the retiming of DC. I will try again.


regards

atuo

 

[horzonbluz]

Usually when we synthesis a design, we set default load cell of our
target library. For exzample, i set my design using INVX1 as default load cell. So i set fanout load 8 [outputs signals] and set port fanout number 4 [outputs signals], you can see if a output port can drive 32 INVX1, its driving ability is enough. These values are set accord to Foundry's library and your need.