Some question on pll jitter

[kooller]

Hi everyone,
I'm study jitter of PLL now, and I found there are cycle to cycle jitter, period jitter, accumulate jitter to discribe jitter in PLL. For PLL, can I say cycle -cycle jitter is smaller than period jitter, and period jitter is smaller than accumulate jitter?

 

[qieda]

Hi,

for my understanding
cycle to cycle jitter is the difference in the cycle width between two consucative clock cycles.
periodic jitter is the difference between the maximum and minimum clock cycle.

so normally periodic jitter is larger than cycle to cycle jitter. It can only be equal if in your system the maximum and minimum clock cylce follow each other.

accumulated jitter for me is the difference of the sum of the period of N cycles following each other compared with the sum of the period of N average clock cycles.

This can be larger or smaller than the periodic jitter depending on your jitter frequency and on the value of N

regards

 

[kooller]

Hi qieda,

Thanks for your reply!

I agree with you comment on cycle to cycle jitter(Jcc).
But I read in paper that:
period jitter(Jp) is the difference between instantaneous peiod with the idea period.
accumulated jitter (Ja,also called long term jitter) is the difference between the instantaneous rising edge with the idea rising edge, that is : tn-n*T.

So Jp=Ja-Ja(n-1).
Jcc=Jp-Jp(n-1).

For PLL, the integral of phase noise represents for RMS value of accumulated jitter.
Because Jp=Ja-Ja(n-1), low frequency offset phase noise will have litter effect on Jp
The will make Jp smaller than Ja, and I have confirmed this by simulation them from phase noise.

But for the relation between period jitter and cycle-cycle jitter, I'm not so certain.

 

[qieda]

Hi,

I think I depend on the kind of jitter you have

first example

we have a clock with ideal period 100ps
so we have a edge at 0ps, 100ps, ....
assuming I have a jitter (Time interval error, TIE) of +-15ps around this ideal edge.

Than
our period jitter (as you mentiond current period - ideal period) could be +- 30ps
our cycle2cycle jitter (as you mentiond current period - previous period) could be +- 60ps
if I use a accumulated jitter over 10 periods I still will have the period jitter (+- 30ps)
-> this is because in this system I do not have a jitter accumulation


second example

we have a clock with ideal period 100ps
so we have a edge at 0ps, 100ps, ....
assuming I have a random jitter (Period jitter) of +-30ps around the ideal period

Than
our period jitter (as you mentiond current period - ideal period) could be +- 30ps (as before)
our cycle2cycle jitter (as you mentiond current period - previous period) could be +- 60ps (as before)
if I use a accumulated jitter over 10 periods I can have in worst case 10 times the period jitter (+- 300ps)


So both systems look quite similar with respect to cycle2cyle jitter and period jitter but this does not give an information about the accumulated jitter.

So I would say
Ja >= Jcc > Jp


regards