some nets not showing up in chipscope

[satya_kola]

Hi

i have code to to calculate pulse width. my code is working fine. I added a chipscop pro to my project.In of net connection window some net's are missing. I declared the output as pw : out STD_LOGIC_VECTOR(31 DOWNTO 0);

but in net connection window it is showing as below

pw_2 pw_2 FDE FDE
pw_3 pw_3 FDE FDE
pw_4 pw_4 FDE FDE
pw_5 pw_5 FDE FDE
pw_6 pw_6 FDE FDE
pw_7 pw_7 FDE FDE
pw_8 pw_8 FDE FDE
pw_9 pw_9 FDE FDE
pw_10 pw_10 FDE FDE
pw_11 pw_11 FDE FDE
pw_12 pw_12 FDE FDE
pw_13 pw_13 FDE FDE
pw_14 pw_14 FDE FDE
pw_15 pw_15 FDE FDE
pw_16 pw_16 FDE FDE
pw_17 pw_17 FDE FDE
pw_18 pw_18 FDE FDE
pw_19 pw_19 FDE FDE
pw_20 pw_20 FDE FDE
pw_21 pw_21 FDE FDE
pw_22 pw_22 FDE FDE
pw_23 pw_23 FDE FDE
pw_24 pw_24 FDE FDE
pw_25 pw_25 FDE FDE
pw_26 pw_26 FDE FDE
pw_27 pw_27 FDE FDE
pw_28 pw_28 FDE FDE
pw_29 pw_29 FDE FDE
pw_30 pw_30 FDE FDE
pw_31 pw_31 FDE FDE


My pw_0 and pw_1 are missing.

and i am unable to synthesis the code some errors are coming. when i synthesis the code without chipscope pro it is fine


error message are

ERRORack:679 - Unable to obey design constraints
(MACRONAME=U_ila_pro_0/U0_I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GA
ND.U_match/I_SRL16.U_GAND_SRL16_MSET, RLOC=X0Y3) which require the
combination of the following symbols into a single SLICEM component:
Shift symbol
"U_ila_pro_0/U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match
/I_SRL16.U_GAND_SRL16/I_TWMOD8_NE0.I_YES_RPM.I_SRLT_EQ_2.U_SRLH" (Output
Signal =
U_ila_pro_0/U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/
I_SRL16.U_GAND_SRL16/sel<31>)
Shift symbol
"U_ila_pro_0/U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match
/I_SRL16.U_GAND_SRL16/I_TWMOD8_NE0.I_YES_RPM.I_SRLT_EQ_2.U_SRLL" (Output
Signal =
U_ila_pro_0/U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/
I_SRL16.U_GAND_SRL16/sel<30>)
MUXCY symbol
"U_ila_pro_0/U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match
/I_SRL16.U_GAND_SRL16/I_TWMOD8_NE0.I_YES_RPM.I_YES_MUXH.U_MUXH" (Output
Signal =
U_ila_pro_0/U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/
I_SRL16.U_GAND_SRL16/I_TWMOD8_NE0.I_YES_RPM.I_YES_MUXH.U_MUXH/O)
The function generator
U_ila_pro_0/U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/
I_SRL16.U_GAND_SRL16/I_TWMOD8_NE0.I_YES_RPM.I_SRLT_EQ_2.U_SRLL is unable to
be placed in the F position because the output signal doesn't match other
symbols' use of the F signal. The signal
U_ila_pro_0/U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/
I_SRL16.U_GAND_SRL16/sel<31> already uses F. Please correct the design
constraints accordingly.


in warning window some warnings are there

WARNING:NgdBuild:1012 - The constraint <INST: UniqueName:
WARNING:NgdBuild:1012 - The constraint <INST: UniqueName:
WARNING:NgdBuild:1012 - The constraint <INST: UniqueName:
WARNING:NgdBuild:1012 - The constraint <INST: UniqueName:
WARNING:NgdBuild:1012 - The constraint <INST: UniqueName:
WARNING:NgdBuild:1012 - The constraint <INST: UniqueName:
WARNING:NgdBuild:1012 - The constraint <INST: UniqueName:
WARNING:NgdBuild:1012 - The constraint <INST: UniqueName:
WARNING:NgdBuild:1012 - The constraint <INST: UniqueName:
WARNING:NgdBuild:1012 - The constraint <INST: UniqueName:
WARNING:NgdBuild:1012 - The constraint <INST: UniqueName:
WARNING:NgdBuild:1012 - The constraint <INST: UniqueName:
WARNING:NgdBuild:1012 - The constraint <INST: UniqueName:

________________________________++++++++++++__________________________________
=======================================================================
WARNING:Xst:1293 - FF/Latch <count_0> has a constant value of 0 in block <pulse_measure>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <count2_0> has a constant value of 0 in block <pulse_measure>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <pri1_0> (without init value) has a constant value of 0 in block <pulse_measure>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <pw_0> (without init value) has a constant value of 0 in block <pulse_measure>. This FF/Latch will be trimmed during the optimization process.




Help me thanks in advance

 

[ads_ee]

Are you using the cs core insertion method or instantiating a core you built with the wizard?

If you use the core insertion method you should use the as synthesized design as the RTL names may no longer be reflected in the synthesized netlist. Also enable rebuilt hierarchy if you don't already have that enabled.

In the case of the two missing bits they may be named something entirely different if they are connected to another level of hierarchy that changes the name. I've seen this type of problem before.

If you instantiate the core with an `ifdef CS_DBG around it you can always enable or disable the insertion by adding the definition into the Process Properties - Synthesis Options dialog box under -defines

I've used both methods, but I prefer to use the instantiated cores when I see that it may be beneficial to have the ability to re-add some verification logic for test purposes.

-alan

 

[satya_kola]

Hey thanks. I understood .
but what about warning window messages. why it is saying WARNING:NgdBuild:1012 - The constraint <INST: UniqueName:

 

[ads_ee]

not sure, the only message "The constraint <INST: UniqueName:" remotely related on Xilinx support is for EDK. NgdBuild:1012 references overridden constraints.

 

[asi123]

Are you getting errors about the constraints?

Make sure the clock you use for chipscope is able to sample the signals you are giving it.

You may have a timing problem.

Assaf.