rakesh_aadhimoolam
Full Member level 4
hello.........
1) if i have two chip design (two FPGA).what timing characteristic of each chip would i need to know in order to compute max. frequency at which data can be transferred between two chips...
2)how can i minimize the required external setup time of internal pin...........
3)what timing constraint am i checking if i compute minimum path delay from external input to input of register.......
1) if i have two chip design (two FPGA).what timing characteristic of each chip would i need to know in order to compute max. frequency at which data can be transferred between two chips...
2)how can i minimize the required external setup time of internal pin...........
3)what timing constraint am i checking if i compute minimum path delay from external input to input of register.......