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some interview questions.........

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rakesh_aadhimoolam

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hello.........

1) if i have two chip design (two FPGA).what timing characteristic of each chip would i need to know in order to compute max. frequency at which data can be transferred between two chips...

2)how can i minimize the required external setup time of internal pin...........

3)what timing constraint am i checking if i compute minimum path delay from external input to input of register.......
 

bigrice911

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(1) chip 1 setup time and chip 2 hold time
 

bansalr

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if i have two chip design (two FPGA).what timing characteristic of each chip would i need to know in order to compute max. frequency at which data can be transferred between two chips...

offset in and offset out of both the FPGA


2)how can i minimize the required external setup time of internal pin...........

Use IOB flip flop to register the data at the output.


3)what timing constraint am i checking if i compute minimum path delay from external input to input of register.......

offset in after
 

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