Re: FLOORPLANNING
1- Where floorplanning step is placed in the design flow ?
In general, the Floorplanning will be after the RTL Synthesised and befor the Placement.
2- What is the percentage of time taken by this task in the ICs design ?
For the PD, the Floorplanning will spend about 15~20% effort. In the whole IC design flow, it should be much less than this.
3- What CAD tools are used for this purpuse and what is their entries files ?
There are some dedicate tools used for Floorplanning, depends on the flow selected by yourself. The entry files will be: Die Size (Estimated), IO Ring, Marco cells, Clock and Power Informations, ... It depends on the detail tool.
Anyone else can give the detail?
4- According to what paramerter floorplan is determined ?
The major information should be: Die Size (Estimated), IO Ring, Marco cells, Clock and Power Informations
5- How to find the best floorplan ?
In general, this is a process of Trade-off. There is bad floorplan, but hard to say best ones.
6- Can you refert me to a practical book on floorplanning ?
Why not read the related tutorials?