Some basic questions about floorplanning

[master_picengineer]

Hi everybody,

Please, can anybody tell me:

1- Where floorplanning step is placed in the design flow ?
2- What is the percentage of time taken by this task in the ICs design ?
3- What CAD tools are used for this purpuse and what is their entries files ?
4- According to what paramerter floorplan is determined ?
5- How to find the best floorplan ?
6- Can you refert me to a practical book on floorplanning ?

I'll be very thankfull if you upload also material on this issue.

Thanks a lot.

Regards,
Master_PicEngineer

 

[littleyard]

Re: FLOORPLANNING

1- Where floorplanning step is placed in the design flow ?
In general, the Floorplanning will be after the RTL Synthesised and befor the Placement.

2- What is the percentage of time taken by this task in the ICs design ?
For the PD, the Floorplanning will spend about 15~20% effort. In the whole IC design flow, it should be much less than this.

3- What CAD tools are used for this purpuse and what is their entries files ?
There are some dedicate tools used for Floorplanning, depends on the flow selected by yourself. The entry files will be: Die Size (Estimated), IO Ring, Marco cells, Clock and Power Informations, ... It depends on the detail tool.

Anyone else can give the detail?

4- According to what paramerter floorplan is determined ?
The major information should be: Die Size (Estimated), IO Ring, Marco cells, Clock and Power Informations

5- How to find the best floorplan ?
In general, this is a process of Trade-off. There is bad floorplan, but hard to say best ones.

6- Can you refert me to a practical book on floorplanning ?
Why not read the related tutorials?

 

[shavakmm]

Re: FLOORPLANNING

the more time you spend in floor plan the less time you may require in later stages...... the reason is modern day SoCs have several IPs and very large in gate count. As said in Synopsys manual (or tutorial) there is no standard "good" or "bad" floorplanning strategies...... it all depends on design tradeoffs and experience of the designer. But even then there are some basic rules which can be followed like "thousand island structure" (i.e IPs are distributed over the core area), Craters Methos (i.e. IPs are concentrated at the corner of core area) and so on...

i request the designers to share their experience in floorplanning of SoC...this would be a great discussion.

 

[salma ali bakr]

Re: FLOORPLANNING

I recommend a very important book for this topic and for the whole ASIC flow in general: Advanced ASIC Chip Synthesis Using Synopsys® Design Compiler® Physical Compiler® and PrimeTime®...it's here on the forum it's a must read...i'm still reading in it!

 

[shavakmm]

Re: FLOORPLANNING

yaa....you are right.... that book from Himanshu Bhatnagar is very good introduction to ASIC design and implementation using Synopsys tool