solving setup time violation

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vivek

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hi
Suppose that im in my design one of the flops is giving setup time violation.
What are the ways in which i can solve it?
 

how much is the violation ?
u can swap with low delay sequential cell .
 

1.over-constrain the design and re-synthesis.
2.pipeline the design in your code
 

hi
if i had got the violation in one of my gate level simulations, what kind of changes should i do in the code? also can u explain how i can pipline my design or over constrain it? Can you give a sample code?
 

Solution is:
1. slow down the clock
2. delay the clock by assert a buffer.
3. choose another FF to avoid violation.
 

Yun Lin said:
Solution is:
1. slow down the clock
2. delay the clock by assert a buffer.
3. choose another FF to avoid violation.
Click to expand...


i have a question about the 2nd solution. Will it cause other timing violations for a synchronous design ? when we do the dc, don't we think the clock network is ideal?
 

1) if the flops input is a asynchronous input, you can disable this flop's

setup checking, that's safe.

2) if the flops input is synchronous, you can:

set DC constraint more stringent.

redesign your code to speed logic.

skew related clocks. (bad method, but sometime can help)




vivek said:
hi
Suppose that im in my design one of the flops is giving setup time violation.
What are the ways in which i can solve it?
Click to expand...
 

(1)size up=> if PR congestion, then
(2)change logic=> doesn't work, then
(3)make latency of CLK=>doesn't work, then
(4)make more pipeline stages=>doesn't work, then
(5)re-coding
 

you can use a fast lib to resynthesis the rtl
 

you can use two method:

1) strengthen your DC constraints.

2) re code your rtl and resynthesize.

best regards





vivek said:
hi
Suppose that im in my design one of the flops is giving setup time violation.
What are the ways in which i can solve it?
Click to expand...
 

Increase compile effort
Repartition design
Insert a delay buffer
Use a faster technology library
Go back to code
 

relax constrains in your design and re-synthesis the codes.
 

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