When your clock and data enters the FPGA, you want the data to be transiting with the rising edge of the clock, right?
If so, then as you have clock skew of 3ns, then one way would be to delay the data also by 3ns, which can be achieved by the SC command:
set_input_delay -clock [get_clocks your_input_clk] -min <min_delay_value_in_ns> [get_ports {data_port_name}]
set_input_delay -clock [get_clocks your_input_clk] -max <max_delay_value_in_ns> [get_ports {data_port_name}]
The max and min values can be set by analyzing the timing path.