SOI Vs Bulk MOS transistor

[Junus2012]

Dear Friends

it is a long time since I am reading that the SOI MOS transistor are superior to the bulk counter part at the higher temperature.

I simulated both under the same voltage and temperature condition and I have found the reverse. the currents of the soi transistor are changing more with the temperature what is going on ??:???:

thank you

 

[dick_freebird]

There's SOI, there's SOI and there's SOI. I've worked in all
flavors and I've worked on high temperature stuff.

A SOI where the junctions bottom against the insulator
eliminates D-B and S-B leakages, which can be a big
deal especially on older large-feature technologies. But
you now have an uncontrolled or poorly controlled back
"gate" interface and your handle bias / doping may not
suffice to keep it under control field-wise; add to this
a (mistaken) belief that digital FDSOI doesn't need
body ties, or that there is no body, and you can expect to
see some parasitic BJT gain on your D-B leakage that
does remain in the gate-abutting drain sidewall.

PDSOI may or may not, depending on depths of device
layer and implants, a bottommed junction. You would at
least expect to be required to use body ties. A non-
bottomed PDSOI will add back the junction leakage but
eliminate exposure to back-gate effects.

Then there's the old school deep bonded and dielectric
isolated technolgoies, bipolar, CMOS and BiCMOS, which
are like bulk as far as the transistor internals, but at
least relieve you of the pervasive and huge well-substrate
leakages.

Simulations of high temp operation are untrustworthy
until you've pulled the transistor data there and refitted
the compact model, discovered what it has "assumed
away" and can't cover, and supplemented those
shortcomings somehow. Believing an extrapolation
from an industrial-temp-range or even mil-temp-range
model fit, is asking for a hard knocks education later.

 

[Junus2012]

I am just wondering id the leakage current are modeled in normal models or not ??

 

[dick_freebird]

In my experience, only the subthreshold conduction, never
have I seen a decent modeling of the nonideal leakage floor
and I know that the older MOS models, at least, totally
ignore generation / recombination currents which become
the big deal at high temp. Not sure about BSIM and later.